Hi!
Ich habe hier eine Tritec WS20L mit OBP-Version 2.22(.3), die mit zwei SM71-Modulen (zusammen oder einzeln, 501-2520) den POST nicht beendet:
SMCC SPARCstation 10/20 UP/MP POST version VRV3.43 (01/09/95)
CPU_#0 TI, STP1021PGA(1.x) 1Mb External cache
CPU_#1 ******* NOT installed *******
CPU_#2 ******* NOT installed *******
CPU_#3 ******* NOT installed *******
<<< CPU_00000000 on MBus Slot_00000000 >>> IS RUNNING (MID = 00000008)
$$$$$ WARNING : No Keyboard Detected! $$$$$
MMU ICACHE_TLB bit pattern Test
MMU ICACHE_TLB context flush Test
MMU ICACHE_TLB region flush Test
MMU ICACHE_TLB segment flush Test
MMU ICACHE_TLB page flush Test
MMU ICACHE_TLB entire flush Test
MMU DCACHE_TLB.RBO_LCK Test
MMU D_cached_level2_PTP_test
MMU I_cached_level2_PTP_test
MMU Cached_root_pointer_PTP0_test
MMU TLB_HIT Test
MMU TLB_MISS Test
MMU TLB_PROBE test
ENDIAN-ness Test with IU_registers
ENDIAN-ness Test with FPU_registers
MMU Context Table Reg Test
MMU Context Register Test
MMU TLB Bit Pattern Tests
MMU Flush Tests
D-Cache RAM Write/Read Test
D-Cache PTAG Write/Read Test
D-Cache STAG Write/Read Test
I-Cache RAM Write/Read Test
I-Cache PTAG Write/Read Test
I-Cache STAG Write/Read Test
I-Cache Flush Test
Cache Flashclear Test
MXCC Register Test
MXCC E-Cache Tag RAM Test
MXCC E-Cache Data RAM Test (1 MB E$ DATA RAM, MXCC_CSR=00000000)
MXCC Non-Cache Block Zero Test
MXCC Non-Cache Block Copy Test
MXCC Cacheable Block Read Test
MXCC Cacheable Block Write Test
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Underflow CEXC Test
FPU SP Divide-by-0 CEXC Test
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU SP UE Trap Priority Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Underflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
FPU DP UE Trap Priority Test
FPU DP CE Trap Priority Test
Memory Address Pattern Test
System Interrupt Regs Tests
PROC0 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC0 User Timer Test
PROC0 Counter/Timer Test
System Counter Test
MSI/MSBI Control Reg Tests
IOMMU CAM NTA Pattern Test
IOMMU TLB NTA Pattern Test
IOMMU CAM TLB Comparator Test
IOMMU TLB Flush Tests
DMA2/MACIO ID Register Test
DMA2/MACIO E_CSR Reg. Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2/MACIO D_CSR Reg. Test
DMA2/MACIO D_ADDR Reg. Test
DMA2/MACIO D_BCNT Reg. Test
DMA2/MACIO D_NADDR Reg. Test
ESP Registers Tests
DMA2/MACIO P_CSR Reg. Test
DMA2/MACIO P_ADDR Reg. Test
DMA2/MACIO P_BCNT Reg. Test
PPORT Registers Tests
DMA2/MACIO PPORT IO Lpbck Tst
DMA2/MACIO PPORT XFR Lbck Tst
TOD Registers Test
Available Memory 0x20000000
Allocating SRMMU Context Table
Context Table allocated, Available Memory 0x1ffc0000
Setting SRMMU Context Register
Context Table allocated, Available Memory 0x1ffc0000
Setting SRMMU Context Table Pointer Register
RAMsize allocated, Available Memory 0x1ffb0000
Allocating SRMMU Level 1 Table
Level 1 Table allocated, Available Memory 0x1ffafc00
Mapping RAM @ 0xffef0000
RAM mapped, Available Memory 0x1ffafa00
Mapping ROM @ 0xffd00000
ROM mapped, Available Memory 0x1ffaf800
Mapping ROM @ 0x00000000
ROM mapped, Available Memory 0x1ffaf000
ttya initialized
Cpu #0 TI,TMS390Z55
Cpu #1 Nothing there
Cpu #2 Nothing there
Cpu #3 Nothing there
Kennt jemand das Problem und evtl. eine Loesung? Leider habe ich keine andere Maschine mit MBus-Slots um die Module darin gegenzutesten. Mit 2*SM50 laeuft das System einwandfrei.
Beim Booten ganz ohne Ram-Module kommt das System nicht mal bis zur ueblichen "Kein Ram in J0201 vorhanden"-Fehlermeldung (den Wortlaut suche ich jetzt mal nicht raus).
