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Windows NT auf SPARC

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escimo:

--- Zitat von: Ten Little Indyans am 06. Dezember 2007, 10:27:47 ---Die UltraSPARC CPUs (= SPARC v9) bieten wohl tatsächlich einen Little-endian Modus, zumindest behauptet GCC dafür Code erzeugen zu können...

--- Ende Zitat ---
Auszug aus dem SPARC Architecture Manual V9:


--- Zitat ---0.3.8 Big- and Little-Endian Byte Orders
Finally, we have provided support for data created on little-endian processors such as the 80x86
family. The architecture allows both user and supervisor code to explicitly access data in littleendian
byte order. It is also possible to change the default byte order to little-endian in user mode
only, in supervisor mode only, or in both. This allows SPARC-V9 to support mixed byte order
systems.

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K Changes From SPARC-V8 to SPARC-V9
SPARC-V9 is complimentary to the SPARC-V8 architecture; it does not replace it. SPARC-V9
was designed to be a higher-performance peer to SPARC-V8.
Application software for the 32-bit SPARC-V8 (Version 8\) microprocessor architecture can execute,
unchanged, on SPARC-V9 systems. SPARC-V8 software executes natively on SPARC-V9-
conformant processors; no special compatibility mode is required.
Changes to the SPARC-V9 architecture since SPARC-V8 are in six main areas: the trap model,
data formats, the registers, alternate address space access, the instruction set, and the memory
model.

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K.3 Little-Endian Support
Data accesses can be either big-endian or little-endian. Bits in the PSTATE register control the
implicit endianness of data accesses. Special ASI values are provided to allow specific data
accesses to be in a specific endianness.

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K.6 Little-Endian Byte Order
In SPARC-V8, all instruction and data accesses were performed in big-endian byte order.
SPARC-V9 supports both big- and little-endian byte orders for data accesses only; instruction
accesses in SPARC-V9 are always performed using big-endian order.
--- Ende Zitat ---

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