Hardware > Sun SPARC
Sun Blade 1000 + festplatten werden nicht mehr erkannt?
r0k:
setenv diag-level max
setenv diag-switch? true
hier der output:
--- Code: ---@(#)OBP 4.2.4 2001/06/13 10:100 Nothing there
Clearing TLBs Done
Probi
Power-On Reset0 Device 1,0 N
Executing Power On SelfTest
{0}Pro
{0}@(#)POST, v4.2.4 2001/06/13 16:12p disk
{0} /export/work/staff/firmware_re/excal-post/excal-post-build-4.2.4/excalibur
Probing /pci@8,600000/pci@1 Device 0 Nothing there
/build (firmware_re)
{0} Device Present register (BBC) showed that
{0} CPU1 not present or dead
{0}Soft POR to the whole system
{0}* Configure I2C controller 0
{0}* Configure I2C controller 1
{0}* I2C Controller Loopback Test
{0}* Read JTag IDs of all ASICs
{0} BBC JTag ID: 1483203b
{0} CPMS JTag ID: 1142903b
{0} CPMS JTag ID: 1142903b
{0} CPMS JTag ID: 1142903b
{0} CPMS JTag ID: 1142903b
{0} CPMS JTag ID: 1142903b
{0} CPMS JTag ID: 1142903b
{0}* Read JTag ID of FCAL
{0} FC-AL JTag ID: 1000a12f
{0}* Probing Seeprom on DIMMs and CPU modules
{0}CPU0 Sensor package temperature 25 oC
{0}WARNING: Temperature sensor on
{0}WARNING: Temperature sensor on UPA1 missing.0000 AFAR: 0000.07ff.ee00.2000
{0}Smart card reader present
{0}* Read parameters from seeproms
Cle
{0} Size/bank(MB) Number of banks8110 SPOR FATAL (CPU) PLL
{0}DIMM 0: 128 2
Membase: 0000.0000.0000.0000
{0}DIMM 1: 128 2
Init CPU arrays Done
{0}DIMM 2: 128 2
Setup TLB Done
MMUs ON
Bl
{0}DIMM 3: 128 2
PC = 0000.07ff.f000.37f8
{0}DIMM 4: 128 2
Decompressing Done
Size
{0}DIMM 5: 128 2ya initialized
Start Reason: Sof
{0}DIMM 6: 128 2OR) (PLL)
{0}CPU 1 ratio: 0imm-fru dimm-fru
{0}System frequency: 150 MHzram idprom
{0}* Load PLL and reset
{0}PLL resetpu-fru tempe
{0}* Configure I2C controller 0otherboard-fru
{0}* Configure I2C controller 1
i2c-bridge
{0}* SoftInt & Interruptfloppy parallel serial
{0}Test walking 1 through softint register
Probing /u
{0}Verify TICK register is counting
{0}Verify TICK register Overflow Device 1,0 Nothing there
{0}Verify TICK Interrupt
Probing /
{0}* Stick & Stick-Compare Reg fp disk
{0}Walk 1/0 STICK Compare register/pci@8,600000 Device 1 pci
{0}Verify STICK register is counting/pci@8,600000/pci@1 Device 0 Nothin
{0}Verify STICK register Overflow
Probing
{0}Verify STICK Interrupt 1 Nothing there
{0}* Measure CPU Clock
P
{0}AFT pin is high0/pci@1 Device 2
{0}Setup Memory Controller
{0}Testing I-TLB Tag Access
{0}Test walking 1 through the registerpci@1 Device 6 Nothing there
{0}Test walking 0 through the register
Probing /pci@8,600000/pci@1 Device
{0}* DMMU Registers
{0}Testing Primary Context
Probing /pci@8,600000/p
{0}Test walking 1 through the register
{0}Testing Secondary Context1 Device 9 Nothing there
{0}Test walking 1 through the register
Probing /pci@8,600000/pci@1
{0}Testing D-TSB there
{0}Test walking 1 through the register
Probing /pci@8,600000/pci@1 Device
{0}Testing D-TLB Tag Access
{0}Test walking 1 through the register1 Device c Nothing there
{0}Testing Virtual Wat
{0}Test address down
Probing /pci@8,
{0}Test cell disturbancefirewire usb keyboard
{0}Test data reliability
{0}Test address line transitionsevice 6 scsi disk tape scsi dis
{0}* 8K DTLB RAM
{0}Test address up
Pr
{0}Test address downevice 1 SUNW,m64B
{0}Test cell disturbance
Probing /
{0}Test data reliabilitything there
{0}Test address line transitionsProbing /pci@8,700000 Device 3
{0}* 4M DTLB TAG
{0}Test address up
Probing /pc
{0}Test address downNothing there
{0}Test cell disturbance
@(#)OBP
{0}Test data reliability
{0}Test address line trans
{0}Test cell disturbance
/build
{0}Test data reliability
{0} Devi
{0}Test address line transitionsthat
{0}* 8K ITLB RAM
{0} CPU
{0}Test address upad
{0}Test address downoft POR to the whole
{0}Test cell disturbance
{0}* Confi
{0}Test data reliability
{0}Test address line transitions 1
{0}* 4M ITLB TAGller Loop{0}WARN
{0}Test address upnsor on UPA0 missi
{0}Test address down
{0}Test cell disturbance
{0}WARNING: Tempe
{0}Test data reliabilitysing
{0}Test address line transitionsrt card reader present
{0}* 8K ITLB
{0}DIMM 2: 128
{0}* E-Cache Global Vars Init
{0}* E-Cache Quick Verification 2
{0}* Ecache TAGS
{0}Test address up 4: 128
{0}Test address down 2
{0}Test cell disturbance
{0}DIMM 5:
{0}Test data reliability 2
{0}Test address line transitions
{0}DIMM 6: 128
{0}* Ecache Address Line
{0}* Partial Ecache InitM 7: 128
{0}* BBC E-Star Registers
{0}* I-Cache RAM
{0}Bank 0 is p
{0}Test address up
{0}* I-Cache TAGS0000000.20000000
{0}Testing I-Cache Tag
{0}Test address upnd system frequenc
{0}Test address down
{0}
{0}Test cell disturbance
{0}CPU 1 ratio: 0
{0}Test data reliabilityem frequency: 150 MHz
{0}Test address line transitionsad PLL and reset
{0}Testing I-Cache Micro Tag
{0}* Configure I2C contr
{0}Test address up
{0}Test address downcontroller 1
{0}Test cell disturbance0}* SoftInt & Interrupt
{0}Test data reliability0}Test walking 1 through
{0}Test address line transitions
{0}Te
{0}* I-Cache Snoop Tagstint register
{0}Test address up
{0}V
{0}Test address downs for each level
{0}Test cell disturbance
{0}Test data r
{0}Test data reliability}Verify TICK register Ov
{0}Test address line transitions
{0}Verify TICK Interrupt
{0}* D-Cache TAGS
{0}* Stick &
{0}Test address up
{0}Test address down/0 STICK Compare reg
{0}Test cell disturbance
{0}Verify
{0}Test data reliabilityng
{0}Test address line transitionsgister Overflow
{0}* D-Cache MicroTagsify STICK Interrupt
{0}Test address up
{0}* Measure C
{0}Test address down
{0}AFT pin
{0}Test cell disturbance
{0}Setup Memory Contro
{0}Test data reliability
{0}* IMMU Register
{0}Test address line transitions-TSB
{0}Test wal
{0}* D-Cache SnoopTagsster
{0}Test address up
{0}Test cell disturbance
{0}Test walking 1 th
{0}Test data reliability
{0}Test address line transitionsext
{0}* W-Cache TAGSthrough the regis
{0}Test address up
{0}Test address down
{0}
{0}Test cell disturbancee register
{0}Test data reliability{0}Testing D-TLB Tag Acc
{0}Test address line transitions}Test walking 1 through the regi
{0}* W-Cache SnoopTAGS
{0
{0}Test address uptchpoint
{0}Test address down0}Test walking 1 thr
{0}Test cell disturbance
{0}Test data reliabilityl Watchpoin
{0}Test data reliabili
{0}Test data reliability
{0}Test address line t
{0}Test address line transitions
{0}* 8K DTLB RAM
{0}* P-Cache TAGS address up
{0}Test address upt address down
{0}Test address downest cell disturbance
{0}Test cell disturbance{0}Test data reliability
{0}Test data reliability{0}Test address line tra
{0}Test address line transitions
{0}* 4M DTLB TAG
{0}* P-Cache SnoopTagss up
{0}Test address upwn
{0}Test address downturbance
{0}Test cell disturbance reliability
{0}Test data reliabilityess line transitions
{0}Test address line transitions 8K DTLB TAG
{0}
{0}* P-Cache Status Data
{0}Test address
{0}Test address up
{0}Test data
{0}* FPU Registers
{
{0}Test walking 1/0 FPU registers
{0}
{0}Test register addressing
{0}Test address up
{0}* FSR
{0}Te
{0}Test walking 1 FSR register
{0}Test cell disturbance
{0}* Ecache RAM
{0}Test
{0}Test address up
{0}Test address downline transitions
{0}Test cell disturbance
{0}* 4M ITLB TAG
{0}Test data reliabilityess up
{0}Test address line transitions
{0}Test cell disturbanc
{0}* Ecache Init
{0}Test
{0}* Correctable Ecache ECC Test
{0}Test address line tr
{0}* Uncorrectable Ecache ECC Test
{0}* 8K ITLB TAG
{0}* Correctable SW Ecache ECC Test
{0}Test address down
{0}* Uncorrectable
{0}Streaming Cache A registersl disturbance
{0}Mondo Interrupt A registersy
{0}T
{0}* Schizo pci A id testns
{0}PCI A Vendor ID 108edress Line
{0}PCI A Device ID 8001 Ecache Init
{0}* Schizo mem testC E-Star Registers
{0}memtst ram data port A}* I-Cache RAM
{0}memtst cam data port A
{0}Test
{0}memtst ram addr port A
{0}Test cell distu
{0}Test address down
{0}memtst ln addr port Acell disturbance
{0}memtst pg addr port Ata reliability
{0}memtst sbuf addr port Ass line transitions
{0}* Schizo merg test
{0}Testing I-Cach
{0}merg_wr 8 byte port A
{0}Test a
{0}merg_wr 4 byte port A
{0}Test address down
{0}merg_wr 2 byte port Ast cell disturbance
{0}merg_wr 1 byte port Ast data reliability
{0}merg_blkwr block port Aaddress line transitions
{0}* Map PCI B space
{0}* I-Cach
{0}* Schizo reg test
{0}Te
{0}PBM B registers
{0}Te
{0}Iommu B registers
{0}Te
{0}Streaming Cache B registers
{0}Test data reli
{0}Mondo Interrupt B registers
{0}Test address line transiti
{0}* Schizo pci B i
{0}memtst enta port B
{0}Test address line t
{0}memtst ln addr port B
{0}* D-C
{0}memtst pg addr port B
{0}Test addres
{0}memtst sbuf addr port Best address down
{0}* Schizo merg testl disturbance
{0}merg_wr 8 byte port Bdata reliability
{0}merg_wr 4 byte port Baddress line transitions
{0}merg_wr 2 byte port B
{0}* D-Cache Sno
{0}merg_wr 1 byte port B
{0}Test address up
{0}merg_blkwr block port Bress down
{0}* Map PCI B si
{0}Verify fetch from memory on read miss
{0}Test address line transitio
{0}Verify write-through on write hit}* W-Cache TAGS
{0}
{0}Verify write-through/fetch on read missddress down
{0}Test ce
{0}Verify set-associativity
{0}Test data rel
{0}* Wcache Functional
{0}Test addr
{0}Verify cacheline fill on write miss
{0}* W-Cache SnoopTAGS
{0}Verify buffering
{0}Test address up
{0}Verify coalescing}Test address down
{0}* Pcache Functionalest cell disturbance
{0}* FPU Functional
{0}Test data rel
{0}Test single and double-precision additioness line transitions
{0}* FPU Move To RegistersnoopTags
{0}Moving SP fp value through all fp registersst address down
{0}Test ce
{0}Moving DP fp value through all fp registersdata reliability
{0}Te
{0}* FPU Branchtransitions
{0}Testing Branching on fcc0{0}* P-Cache Status Data
{0}Verify branching
{0}Test address up
{0}Verify no branchingest address down
{0}Testing Branching on fcc1isturbance
{0}* FSR
{0}Verify no branchingFSR register
{0}* Ecache Functional}* Ecache RAM
{0}Verify cacheline fill on read miss
{0}Test address down
{0}Verify write allocate on write miss
{0}Test data relia
{0}Verify cacheline update on write hitddress line transitions
{0}Verify write back Ecache Init
{0}POST_END* Correctab
@(#)OBP 4.2.4 2001/06/13 10:10
{0}* Uncorr
Clearing TLBs DoneTest
POST Results: Cpu 0
{0}* Correctable S
%o0 0000.0000.0000.0000
%o1 0000.07ff.f015.0bd8e ECC Test
%o2 0000.0000.0000.0000Correctable System ECC
MMUs ONters
Copy Done
PC = 0000.07ff.f000.37f8.0011a954
PC = 0000.0000.0000.3878Map PCI A space
Decompressing Donehizo reg test
Size = 0000.0000.0006.e3e0gisters
ttya initializeders
Start Reason: Initialize Machineters
Configuring the machine:gisters
ý
@(#)OBP 4.2.4 2001/06/13 10:10 test
Clearing TLBs Done 108e
Loading Configurationvice ID 8001
Membase: 0000.0000.0000.0000m test
{
MemSize: 0000.0000.8000.0000
{0}memt
Init CPU arrays Done
Init E$ tags Doneddr port A
Setup TLB Done
{0}memtst
MMUs ON port A
Block Scrubbing Done
{0}memtst pnta
Copy Don
Probing gptwo at 0,0 SUNW,UltraSPARC-III (750 MHz @ 5:1, 8 MB)ort A
{0}merg_wr 2 byte port A
memory-controllererg_wr 1 byte port A
Probing gptwo at 1,0 Nothing therekwr block port A
Probing gptwo at 8,0 pci pci upa ppm
{0}* Schizo reg test
Loading Support Packages: kbd-translator
{0}Iommu B registers
Loading onboard drivers: ebus flashprom bbc ppm i2c dimm-fru dimm-fru
{0}Mondo Interrupt B registers
dimm-fru dimm-fru dimm-fru dimm-fru dimm-fru dimm-fru nvram idprom108e
{0}PCI B Device ID 80
CPU 0 set junction power off temperature to 110 degrees CB
{0}memtst ln addr port B
Memory Configuration:0}memtst pg addr por
Segment @ Base: 0 Size: 2048 MB ( 4-Way)ort B
{0}* Schizo merg
Probing /upa@8,480000 Device 0,0 Nothing theret B
{0}merg_wr 4 byte
Probing /upa@8,480000 Device 1,0 Nothing theree port B
{0}merg_wr 1
Probing /pci@8,600000 Device 4 SUNW,qlc fp disk block port B
{0}* M
Probing /pci@8,600000 Device 1 pci
{0}* RIO Config
Probing /pci@8,600000/pci@1 Device a Nothing there
{
Probing /pci@8,600000/pci@1 Device b Nothing there
{0}Test single
Probing /pci@8,600000/pci@1 Device c Nothing there
{0}Test single and double-precision a
Probing /pci@8,600000/pci@1 Device d Nothing therengle and double-precision conversion
Probing /pci@8,600000/pci@1 Device e Nothing thereisters
{0}Moving SP fp va
Probing /pci@8,600000/pci@1 Device f Nothing there
{0}Moving DP fp value throug
Probing /pci@8,700000 Device 5 network firewire usb keyboard
{0}* FPU Branch
{0}Testing Branching on fcc0
Probing /pci@8,700000 Device 6 scsi disk tape scsi disk tape
{0}Verify no branching
{0}Testing
Probing /pci@8,700000 Device 1 SUNW,m64B
{0}Verify branching
Probing /pci@8,700000 Device 2 Nothin
{0}Testing Bran
Reset: 0000.0000.0000.0010 SPOR
Loading Configurationate on write miss
Membase: 0000.0000.0000.0000
{0}Verify cacheline up
MemSize: 0000.0000.8000.0000
Init CPU arrays Done
Init E$ tags Done
@(#)OBP 4.2
Setup TLB Done0:10
MMUs ON
Block Scrubbing Doneone
Copy Doneults: Cpu
PC = 0000.07ff.f000.37f8o0 0000.0000.0000.0000
PC = 0000.0000.0000.3878
%o1 0000.07ff.f015.0
Decompressing Done
%o2
Size = 0000.0000.0006.e3e0
Membase
ttya initialized0000
Start Reason: Soft Reset0000.0000.0010.0000
System Reset: (SPOR)
Init CPU arrays Do
Probing gptwo at 0,0 SUNW,UltraSPA
Probing /upa@8,480000 Device 0,0 Nothing there
Probing /upa@8,480000 Device 1,0 Nothing theregptwo at 1,0 Nothing there
Probing /pci@8,600000/pci@1 Device 1 Nothing there
Probing /pci@8,600000/pci@1 Device 2 Nothing there
Probing /pci@8,600000/pci@1 Device 3 Nothing there
Probing /pci@8,600000/pci@1 Device 4 scsi sd st
Probing /pci@8,600000/pci@1 Device 5 scsi sd st
Probing /pci@8,600000/pci@1 Device 6 Nothing there
Probing /pci@8,600000/pci@1 Device 7 Nothing there
Probing /pci@8,600000/pci@1 Device 8 Nothing there
Probing /pci@8,600000/pci@1 Device 9 Nothing there
Probing /pci@8,600000/pci@1 Device a Nothing there
Probing /pci@8,600000/pci@1 Device b Nothing there
Probing /pci@8,600000/pci@1 Device c Nothing there
Probing /pci@8,600000/pci@1 Device d Nothing there
Probing /pci@8,600000/pci@1 Device e Nothing there
Probing /pci@8,600000/pci@1 Device f Nothing there
Probing /pci@8,700000 Device 5 network firewire usb keyboard
Probing /pci@8,700000 Device 6 scsi disk tape scsi disk tape
Probing /pci@8,700000 Device 1 SUNW,m64B
Probing /pci@8,700000 Device 2 Nothing there
Probing /pci@8,700000 Device 3 Nothing there
Probing /pci@8,700000 Device 4 Nothing there
--- Ende Code ---
Mir ist auch aufgefallen das die Luefter sehr laut sind.
Ebbi:
Kann mal bitte ein Mod diese Ausgabe in [code ] Tags packen?
Das ist ja mehr als lästig. ::)
maal:
Hallo,
das laute Lüftergeräusch ist normal, denn die Drehzahl wird erst bei laufendem Betriebssystem reduziert.
@(#)OBP 4.2.4 2001/06/13 10:10
@(#)POST, v4.2.4 2001/06/13 16:12
Beide Versionen sind so veraltet, daß es sich wahrscheinlich um den Auslieferungszustand handelt. Aktuell sind OBP 4.16.4,POST 4.16.3 und OBDIAG 4.16.4.
{0}WARNING: Temperature sensor on
{0}WARNING: Temperature sensor on UPA1 missing.0000 AFAR: 0000.07ff.ee00.2000
Das könnte ein Hardwaredefekt sein oder aber auch nur seine Ursache in der sehr alten Firmware haben. Die {0} bedeutet aktive/boot CPU ist die erste, was aber eigentlich nur kommt wenn auch 2 CPUs installiert sind. Evtl. ist die zweite CPU doch installiert, aber nicht richtig festgeschraubt.
Die restlichen Tips (Speicher, Kabel und CPU überprüfen) aus dem anderen Forum solltest du auch noch probieren.
set-defaults am ok-prompt macht evtl. falsche Einstellungen rückgängig.
Im ROM befindet sich auch ein interaktives Diagnose-Programm OBDIAG. Wie man es benutzt steht im Handbuch (Sun Blade™ 1000 Service Manual, Part-No 805-4496, Kapitel 4.8.1, Seite 4-12ff).
Wenn das alles nichts hilft, dürfte ein neues Systemboard fällig sein.
Michael
r0k:
Mit dem Lüftergeräusch ist schonmal beruhigend.
Das könnte gut sein, das da noch alles im Auslieferungszustand ist. Ich würde gerne OBP,POST und OBDIAG updaten aber ich hab sowas noch nie gemacht und ich denke dazu brauch ich erstmal ein funktionierendes OS?
Das Manual hab ich schon hier liegen in PDF Form. Ich schau da gleich nochmal rein wegen OBDIAG.
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